As the devices used in integrated circuits continue to shrink in size, the method of shallow trench isolation (STI) has been widely used in preference to the earlier method known as local oxidation of silicon (LOCOS). In practice, the dimensions of trenches that are to be filled can vary significantly. In particular, it is possible that some of the trenches may have very small widths, as low as about 3,000 Angstroms. Special deposition methods need to be used to fill such narrow trenches. An example of this is the method known as HDPCVD. (High density plasma chemical vapor deposition) wherein conventional CVD is combined with bias sputtering. In this manner, atoms or molecules that are not tightly bound are re-sputtered before they get incorporated into the growing film. The result is a very dense material comparable, in the case of deposited oxide, to an oxide layer grown by thermal oxidation.
In practice, it is always necessary to over-fill the trenches and to then etch back until the trenches have just been filled. This is not of itself a problem unless the surface between the trenches has been coated with a hard material such as, for example, silicon nitride. FIG. 1 shows an example of such a situation. Silicon body 10 has an upper surface of silicon nitride 12 (underlaid by a thin layer of pad oxide for the purpose of stress reduction). Trenches 13 and 14 of different sizes have been etched into the surface of 10. FIG. 2 shows the result of covering silicon body 10 with a layer of HDPCVD oxide. All trenches have been over-filled so that there is an excess amount of layer 15 above the the silicon nitride.
The practice of the prior art would now be to use CMP to planarize the surface. Because of the hardness of the material directly above the silicon nitride as compared to material over the trenches, the appearance of the structure after CMP is as shown in FIG. 3. As can be seen, considerable dishing 34 has occurred over the wider trench. Little or no dishing has occurred over the narrower trench 33 because the advance of the etch front will be dominated by the silicon nitride surface on each side. Thus, the problem which the present invention seeks to solve is how to combine the HDPCVD deposition method with the CMP material removal method.
In our search for prior art we came across a number of references to HDPCVD oxide, to CMP, and to etch-back but none of these describe the process of the present invention. Several of these references were of interest, however. For example Jain in two patents of a divisional (U.S. Pat. No. 5,494,854 February 1996 and U.S. Pat. No. 5,621,241 April 1997) describes using HDPCVD together with CMP in connection with planarizing dielectric deposited over metal wiring. Yano et al. (U.S. Pat. No. 5,721,173 February 1998) shows methods of planarizing shallow trenches by means of a selective etch back process. Wang et al. (U.S. Pat. No. 5,175,122 December 1992) show a process involving planarization and etch back as do Peschke et al. (U.S. Pat. No. 5,663,107 September 1997).